Question #5: Which of the following statements is false regarding Paging and Translation Look-aside Buffer (TLB)?
A) Paging requires at least two memory accesses (one to fetch the correct virtual to physical address translation & second to do the actual load/store at the memory location in the instruction).
B) To speed up the first memory access (translation phase), hardware support in the form of MMU and TLB is added.
C) TLB is just a hardware cache for popular virtual to physical address translations.
D) TLB replaces the need to go to page table and thus we don’t need to store page tables for address translation anymore.
Solution: TLB doesn’t replace page tables. Each translation is first checked in TLB, if found it is resolved faster. If it is not found, then page tables need to be searched. Size of TLB is very small and it only contains a few of the popular translations, full information is in the page tables. Hence the correct option is D.
Bytes of the day 